As semiconductor processing technology improvements continue to allow for smaller and smaller device sizes, a number of issues arise. For example, while smaller storage elements in volatile or non-volatile memory allow for greater storage density and lower costs per unit of data storage, the small size of the individual storage elements can lead to an increase in data errors, such as various refresh time errors (also known as various retention time errors), soft errors, single event upset errors, and so forth. In some examples, physical damage to the storage elements (e.g., due to improper manufacturing of the element) can also lead to data errors, but the errors may be distributed such that utilizing repair regions may be ineffective. These soft or hard data errors corrupt data and are typically randomly distributed.
One method for mitigating the effects of these data errors is to store error correction code (“ECC”) parity information (hereinafter referred to as “parity code”) together with the data, and to decode the parity code when the data is read out in order to detect and/or correct any errors in the original data or the added parity code. The parity code requires some overhead both in the amount of data stored (due to the extra bits for the parity code) and in the amount of processing time required for writing to and reading from the data storage device (due to the processing time to encode and decode the ECC parity code). Nonetheless, using ECC is still generally considered to be effective and efficient in detecting and correcting randomly distributed data errors.
Some data storage devices support a data mask option whereby during a write operation, one or more portions of a stored data word retain previous data values while one or more other portions of the data word are updated with new data values. As used herein, a data word refers to a plurality of bits of information, which are normally handled or stored together as a unit, although a data mask option may cause one or more portions of the data word to be handled or stored differently from the other portion(s) of the data word. For example, in a memory, a data word stored at a particular address may include 128 bits of data, and the data mask option during a memory write operation may prevent one or more 8 bit portions of the data word from being updated from the write operation. As an even more specific example, the last 8 bits of the 128 bit data word may be masked in that only the first 120 bits of data will be written to the memory array, with the last 8 bits retaining whatever value they had prior to the write operation.
Implementing ECC in a storage device without a data mask option, during a write operation is fairly straightforward because the data word and parity code to be written are not dependent on prior stored data, but are entirely a function of the new data to be written to the device. However, in a data storage device with a data mask option available, the masked portions of the data word may contain one or more errors that need to be corrected before that old data can be properly merged with the new data as required by the data mask. Also, in order to properly encode the parity code for the merged data word during the write with data mask operation, the masked portion(s) should be taken into consideration by the ECC encoder, and those masked portions should be corrected before the ECC encoder can generate the new parity code. In other words, the parity code for the merged data word is dependent not only on the new portions of the data word but also on the portions of the corrected old data word that are being masked.
In order to address this dependency, one solution may be to read out the old data word and old parity code, decode the old parity code, correct any errors in the old data word based on the decode, and then, subsequently, merge the new portion of the data word with the corrected old portions of the data word, generate a new parity code, and write the merged data word with the new parity code to the storage device. This sequential order of operations, however, may be unacceptable in some instances because the ECC decode and ECC encode operations can be relatively long and the ECC encode operation waits for the ECC decode and correction operation to complete before the new parity code can be generated and stored.
Another approach to address the data mask option in a device with ECC may be to have separate parity codes for each portion of the data word amenable to being masked. For example, continuing with the illustration of a 128 bit data word in which each 8 bit portion may be masked, each 8 bit portion of the data word may be assigned its own parity code, independent from the parity codes of each of the other 8 bit portions. When a write with data mask operation is performed, the masked portions can undergo ECC decode and correction independently of the ECC encode of the new, non-masked portions. In this approach, while sequential ECC operations are avoided, the amount of overhead in both storage space and processing power is increased. Using the 128 bit example, each 8 bit portion may have a parity code that is 4 bits long, thus requiring a total of 64 parity bits (50% overhead), and 16 independent ECC encode/decode circuits may be needed to separately encode or decode the parity codes for each 8 bit portion. In comparison, for the sequential approach described above, only 8 parity bits may be required for the 128 bit data word (6.25% overhead), and a single ECC circuit may both decode/correct and encode the parity codes, because the ECC encode operation cannot proceed until the ECC decode operation is complete.